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Very Low Power CMOS SRAM 32K X 8 bit
Pb-Free and Green package materials are compliant to RoHS
BS62LV256
n FEATURES
Y Wide VCC operation voltage : 2.4V ~ 5.5V Y Very low power consumption : VCC = 3.0V Operation current : 25mA (Max.) at 70ns 1mA (Max.) at 1MHz Standby current : 0.01uA(Typ.) at 25OC VCC = 5.0V Operation current : 40mA (Max.) at 55ns 2mA (Max.) at 1MHz Standby current : 0.4uA (Typ.) at 25OC Y High speed access time : -55 55ns(Max.) at VCC : 4.5~5.5V -70 70ns(Max.) at VCC : 3.0~5.5V Y Automatic power down when chip is deselected Y Easy expansion with CE and OE options Y Three state outputs and TTL compatible Y Fully static operation Y Data retention supply voltage as low as 1.5V
n DESCRIPTION
The BS62LV256 is a high performance, very low power CMOS Static Random Access Memory organized as 32,768 by 8 bits and operates form a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 0.01uA and maximum access time of 70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable (CE), and active LOW output enable (OE) and three-state output drivers. The BS62LV256 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV256 is available in DICE form, JEDEC standard 28 pin 330mil Plastic SOP, 600mil Plastic DIP, 8mmx13.4mm TSOP (normal type).
n POWER CONSUMPTION
POWER DISSIPATION PRODUCT FAMILY
BS62LV256DC BS62LV256PC BS62LV256SC BS62LV256TC BS62LV256PI BS62LV256SI BS62LV256TI Industrial -40OC to +85OC 5.0uA 0.7uA 2mA 20mA 40mA 1mA 15mA 25mA Commercial +0OC to +70OC 4.0uA 0.4uA 1.5mA 18mA 35mA 0.8mA 12mA 20mA
OPERATING TEMPERATURE
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
PKG TYPE
VCC=3.0V 10MHz fMax.
VCC=5.0V
VCC=3.0V
1MHz
VCC=5.0V 10MHz
fMax.
1MHz
DICE PDIP-28 SOP-28 TSOP-28 PDIP-28 SOP-28 TSOP-28
n PIN CONFIGURATIONS
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14
n BLOCK DIAGRAM
28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
*
BS62LV256PC BS62LV256PI BS62LV256SC BS62LV256SI
A5 A6 A7 A12 A14 A13 A8 A9 A11
Address Input Buffer
9
Row Decoder
512
Memory Array
512X512
512 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 8 Data Input Buffer 8 64 Column Decoder 6 CE WE OE VCC GND A4 A3 A2 A1 A0 A10 Control Address Input Buffer 8 Column I/O Write Driver Sense Amp
8
Data Output Buffer
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
BS62LV256TC BS62LV256TI
28 27 26 25 24 23 22 21 20 19 18 17 16 15
A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS62LV256
1
Revision 2.6 Sep. 2006
BS62LV256
n PIN DESCRIPTIONS
Name
A0-A14 Address Input CE Chip Enable Input
Function
These 15 address inputs select one of the 32,768 x 8-bit in the RAM
CE is active LOW. Chip enable must be active when data read form or write to the device. If chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive. There 8 bi-directional ports are used to read data from or write data into the RAM.
WE Write Enable Input
OE Output Enable Input
DQ0-DQ7 Data Input/Output Ports VCC GND
Power Supply
Ground
n TRUTH TABLE MODE
Not selected (Power Down) Output Disabled Read Write
CE
H L L L
WE
X H H L
OE
X H L X
I/O OPERATION
High Z High Z DOUT DIN
VCC CURRENT
ICCSB, ICCSB1 ICC ICC ICC
NOTES: H means VIH; L means VIL; X means don't care (Must be VIH or VIL state)
n ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM TBIAS TSTG PT IOUT
(1)
n OPERATING RANGE
UNITS
V
O
PARAMETER
Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
RATING
-0.5(2) to 7.0 -40 to +125 -60 to +150 1.0 20
RANG
Commercial Industrial
AMBIENT TEMPERATURE
0OC to + 70OC -40OC to + 85OC
VCC
2.4V ~ 5.5V 2.4V ~ 5.5V
C C
O
W mA
n CAPACITANCE
(1)
(TA = 25 C, f = 1.0MHz)
O
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
CIN CIO Input Capacitance Input/Output Capacitance VIN = 0V VI/O = 0V 6 8 pF pF
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. -2.0V in case of AC pulse width less than 30 ns. R0201-BS62LV256
1. This parameter is guaranteed and not 100% tested.
2
Revision 2.6 Sep. 2006
BS62LV256
n DC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C)
PARAMETER NAME VCC VIL VIH IIL ILO VOL VOH ICC(5) ICC1 ICCSB ICCSB1(6) PARAMETER
Power Supply
O O
TEST CONDITIONS
MIN.
2.4 -0.5(2)
TYP.(1)
--
MAX.
5.5
UNITS
V
Input Low Voltage
--
0.8 VCC+0.3(3)
V
Input High Voltage
2.2
--
V
Input Leakage Current
VIN = 0V to VCC CE= VIH, or OE = VIH, VI/O = 0V to V CC
--
--
1
uA
Output Leakage Current
--
--
1
uA
Output Low Voltage
V CC = Max, IOL = 0.5mA
--
--
0.4
V
Output High Voltage Operating Power Supply Current Operating Power Supply Current Standby Current - TTL
V CC = Min, IOH = -0.5mA CE = VIL, IDQ = 0mA, f = CE = VIL, IDQ = 0mA, f = 1MHz CE = VIH, IDQ = 0mA FMAX(4)
VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V
2.4 ---------
-------0.01 0.4
-25 40 1 2 1.0 2.0 0.7 5.0
V
mA
mA
mA
Standby Current - CMOS
CEVCC-0.2V, VINV CC-0.2V or VIN0.2V
uA
1. Typical characteristics are at TA=25OC and not 100% tested. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. FMAX=1/tRC. 5. ICC (MAX.) is 20mA/35mA at VCC=3.0V/5.0V and TA=70OC. 6. ICCSB1(MAX.) is 0.4uA/4.0uA at VCC=3.0V/5.0V and TA=70OC.
n DATA RETENTION CHARACTERISTICS (TA = -40 C to +85 C)
SYMBOL VDR ICCDR(3) tCDR tR PARAMETER
VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
O
O
TEST CONDITIONS
CEVCC-0.2V, VINVCC-0.2V or VIN0.2V CEVCC-0.2V, VINVCC-0.2V or VIN0.2V
MIN.
1.5 -0
TYP. (1)
-0.01 ---
MAX.
-0.7 ---
UNITS
V uA ns ns
See Retention Waveform tRC (2)
1. VCC=1.5V, TA=25OC and not 100% tested. 2. tRC = Read Cycle Time. 3. ICCDR(Max.) is 0.4uA at TA=70OC.
n LOW VCC DATA RETENTION WAVEFORM (CE Controlled)
Data Retention Mode
VCC
VIH
VCC
VDR1.5V
VCC
tCDR
CEVCC - 0.2V
tR
VIH
CE
R0201-BS62LV256
3
Revision 2.6 Sep. 2006
BS62LV256
n AC TEST CONDITIONS
(Test Load and Input/Output Reference) WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM "H" TO "L" MAY CHANGE FROM "L" TO "H" DON'T CARE ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM "H" TO "L" WILL BE CHANGE FROM "L" TO "H" CHANGE : STATE UNKNOW CENTER LINE IS HIGH INPEDANCE "OFF" STATE
n KEY TO SWITCHING WAVEFORMS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level tCLZ, tOLZ, tCHZ, tOHZ, tWHZ Output Load Others
Vcc / 0V 1V/ns 0.5Vcc CL = 5pF+1TTL CL = 100pF+1TTL ALL INPUT PULSES
1 TTL Output CL(1)
VCC GND
10%
90%
90% 10%
Rise Time : 1V/ns
Fall Time : 1V/ns
1. Including jig and scope capacitance.
n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) READ CYCLE
JEDEC PARAMETER NAME PARANETER NAME CYCLE TIME : 55ns (VCC = 4.5~5.5V) MIN. TYP. MAX. 55 ---10 10 --10 ----------55 55 25 --30 25 -CYCLE TIME : 70ns (VCC = 3.0~5.5V) MIN. TYP. MAX. 70 ---10 10 --10 ----------70 70 35 --35 30 --
O
O
DESCRIPTION
UNITS
tAVAX tAVQX tE1LQV tGLQV tE1LQX tGLQX tE1HQZ tGHQZ tAVQX
tRC tAA tACS tOE tCLZ tOLZ tCHZ tOHZ tOH
Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Output Enable to Output Low Z Chip Select to Output High Z Output Enable to Output High Z Data Hold from Address Change
ns ns ns ns ns ns ns ns ns
R0201-BS62LV256
4
Revision 2.6 Sep. 2006
BS62LV256
n SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1
(1,2,4)
tRC ADDRESS tOH DOUT tAA tOH
READ CYCLE 2
(1,3,4)
CE tACS tCLZ DOUT
(5)
tCHZ
(5)
READ CYCLE 3
(1, 4)
tRC ADDRESS tAA OE tOE CE
(5)
tOH
tOLZ tACS tCLZ tOHZ tCHZ
(5) (1,5)
DOUT
NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Transition is measured 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested.
R0201-BS62LV256
5
Revision 2.6 Sep. 2006
BS62LV256
n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) WRITE CYCLE
JEDEC PARAMETER NAME PARANETER NAME CYCLE TIME : 55ns (VCC = 4.5~5.5V) MIN. Write Cycle Time Address Valid to End of Write Chip Select to End of Write Write Pulse Width Address Set up Time Write Recovery Time Write to Output High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (CE, WE) 55 55 55 35 0 0 -35 0 -5 TYP. -----------MAX. ------25 --25 -CYCLE TIME : 70ns (VCC = 3.0~5.5V) MIN. 70 70 70 40 0 0 -40 0 -5 TYP. -----------MAX. ------30 --30 -ns ns ns ns ns ns ns ns ns ns ns
O O
DESCRIPTION
UNITS
tAVAX tAVWH tE1LWH tWLWH tAVWL tWHAX tWLQZ tDVWH tWHDX tGHQZ tWHQX
tWC tAW tCW tWP tAS tWR tWHZ tDW tDH tOHZ tOW
n SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1
(1)
tWC ADDRESS tWR OE tCW CE
(5) (11) (3)
tAW WE tAS tOHZ DOUT tDH tDW DIN
(4,10)
tWP
(2)
R0201-BS62LV256
6
Revision 2.6 Sep. 2006
BS62LV256
WRITE CYCLE 2
(1,6)
tWC ADDRESS tCW
(11)
CE
(5)
tAW WE tAS tWHZ DOUT
(4,10)
tWP
(2)
tOW tDW tDH
(8,9)
(7)
(8)
DIN
NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. tWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 11. tCW is measured from the later of CE going low to the end of write.
R0201-BS62LV256
7
Revision 2.6 Sep. 2006
BS62LV256
n ORDERING INFORMATION
BS62LV256
X
X
Z
YY
SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE D: DICE S: SOP T: TSOP (8mm x 13.4mm) P: PDIP
Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
0.020 0.005X45
b
WITH PLATING
c c1
BASE METAL
b1
SOP - 28
R0201-BS62LV256
8
Revision 2.6 Sep. 2006
BS62LV256
n PACKAGE DIMENSIONS (continued)
12(2x) 12(2x)
UNIT SYMBOL
INCH 0.04330.004 0.00450.0026 0.0390.002 0.0090.002 0.0080.001 0.004 ~ 0.008 0.004 ~ 0.006 0.4650.004 0.3150.004 0.0220.004 0.5280.008 0.0197 +0.008 - 0.004 0.03150.004 0.004 Max. 0~ 8
MM 1.100.10 0.1150.065 1.000.05 0.220.05 0.200.03 0.10 ~ 0.21 0.10 ~ 0.16 11.800.10 8.000.10 0.550.10 13.400.20 0.50 +0.20 - 0.10 0.800.10 0.1 Max. 0~ 8
A A1
HD e
cL
1 28 E
A2 b b1
b
c c1 D E
Seating Plane y
e
14 15 12(2x)
HD L L1
GAUGE PLANE
"A"
D
A
A2 A 0.254 0 A1
y 0
14
15
SEATING PLANE 12(2x) L
A
"A" DATAIL VIEW
L1
WITH PLATING
b
1
28
c c1 b1
BASE METAL
SECTION A-A
TSOP - 28
PDIP - 28
R0201-BS62LV256
9
Revision 2.6 Sep. 2006
BS62LV256
n Revision History Revision No. 2.4 2.5 History Add Icc1 characteristic parameter Change I-grade operation temperature range - from -25OC to -40OC Revised ICCSB1 sepc. - from 1.0uA to 4.0uA for 5V C-grade - from 2.0uA to 5.0uA for 5V I-grade - from 0.2uA to 0.4uA for 3V C-grade - from 0.4uA to 0.7uA for 3V I-grade Revised ICCDR sepc. - from 0.2uA to 0.4uA for C-grade - from 0.4uA to 0.7uA for I-grade Draft Date Jan. 13, 2006 May. 25, 2006 Remark
2.6
Sep. 05, 2006
R0201-BS62LV256
10
Revision 2.6 Sep. 2006

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